1. Field
The present application generally relates to test cells for analyzing semiconductor manufacturing processes, and, more particularly, to test cells to detect and localize defect to improve yield in semiconductor manufacturing processes.
2. Description of Related Art
The fabrication of integrated circuits is a complex process that may involve hundreds of individual operations. The process typically includes the diffusion of precisely predetermined amounts of dopant material into portions of a silicon wafer to produce active regions for producing junctions to be used in devices, such as transistors. Some steps of the process include forming a layer of silicon dioxide on the wafer, then using a photomask and photoresist to define a pattern of areas into which diffusion is to occur through the silicon dioxide mask. Openings may then be etched through the silicon dioxide layer to expose portions of the wafer in the pattern to permit dopant diffusion into those wafer portions.
A number of diffusion operations may be carried out to produce active regions on the wafer for a variety of transistors. Through further processing steps, some of these active regions are coupled to metal interconnects, while other active regions may be covered by a silicon dioxide insulating layer and exposed to electric fields from a line disposed above each region. Such lines and interconnects are typically formed by deposition of electrically conductive material that is defined into a desired interconnect pattern by photomask, photoresist and etching processes.
In exemplary current processes, there may be 10 interconnect layers (“metal layers”) with a polysilicon (“poly”) gate line disposed over an active region of a transistor. Features disposed at layers connecting one interconnect layer to another interconnect layer (either above or below a given layer) are called vias. Features disposed at layers connecting one interconnect layer to semiconductor active regions are called contacts.
Traditionally, proper functioning of these layers is measured with test structures on a test chip. Test structures for via/contact opens are usually chains of vias/contacts connected serially end to end. A high resistance along is interpreted to mean that there is a via/contact open somewhere in this chain. Test structures for metal opens are usually a long snake of wiring connected at the ends; a high resistance on this snake indicates that there is an open in the snake.
Test structures for short circuits include two combs of wiring connected at either end. A voltage is applied to one comb and current is sensed at the other comb. A significant current above some noise floor indicates a short between the two combs.
These structures are useful for increasing process yield but have limited capabilities. One major limitation relates to defect localization. For defect localization, semiconductor manufacturers typically use some form of physical de-layering followed by other emission or sensitive detection method. Electron microscopy images may be obtained and analyzed for determining a cause of failure.
SRAM memory arrays have also been an aid in localizing defects. A memory array is composed of many rows and columns of memory elements. By constructing such a memory array and analyzing patterns of memory element failure, some information relating to a likely failure layer may be determined. However, this information does not typically result in a complete understanding of failure mode since similar failure symptoms may be caused by a wide variety of different problems.